VLSI

   

FPGA Implementation Technology for Memory Efficient Hardware Architecture


Definition

VLSI stands for Very Large Scale Integration; it is the process of creating an Integrated Circuit which is called as IC, by combining thousands of transistors into a single chip. This Technology not only helped to reduce the size of the devices but also improved their speed. By using this, we can implement a real time application Projects.

Uses

With the Knowledge of VLSI, we can implement a Project in the field of Voice and Data Communication networks, Digital Signal Processing, Automobiles, Commercial Electronics, and Medical Electronics. These are all implementing with the standard of IEEE.

Benefit

By choosing this technology, the student can empower their academic skills for their bright career with Knowledge. Especially for Final year B.E. and Polytechnic students in the department of ECE.


 

S.No Code Title Year Download
1 ETSVL007- 2017 VLSI Extreme Learning Machine: A Design Space Exploration 2017 Abstract | Basepaper
2 ETSVL006- 2017 Single-Objective Path Planning For Autonomous Robots Using Reconfigurable Analog VLSI 2017 Abstract | Basepaper
3 ETSVL005- 2017 A Cost And Power Efficient Image Compressor VLSI Design With Fuzzy Decision And Block Partition For Wireless Sensor Networks 2017 Abstract | Basepaper
4 ETSVL004- 2017 Optimal VLSI Delay Tuning By Space Tapering With Clock-Tree Application 2017 Abstract | Basepaper
5 ETSVL003- 2017 Hardware/Software Co-Design And VLSI Implementation For The Intelligent Surveillance System 2017 Abstract | Basepaper
6 ETSVL002- 2017 Univariate Power Analysis Attacks Exploiting Static Dissipation Of Nanometer CMOS VLSI Circuits For Cryptographic Applications 2017 Abstract | Basepaper
7 ETSVL033-2016 VLSI Computational Architectures For The Arithmetic Cosine Transform 2016 Abstract | Basepaper
8 ETSVL032-2016 Skewed-Load Test Cubes Based On Functional Broadside Tests For A Low-Power Test Set 2016 Abstract | Basepaper
9 ETSVL028-2016 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding 2016 Abstract | Basepaper
10 ETSVL027-2016 Piecewise-Functional Broadside Tests Based On Reachable States Irith Pomeranz 2016 Abstract | Basepaper
11 ETSVL034-2016 Partially Parallel Encoder Architecture For Long Polar Codes 2016 Abstract | Basepaper
12 ETSVL025-2016 One Minimum Only Trellis Decoder For Non-Binary Low-Density Parity-Check Codes 2016 Abstract | Basepaper
13 ETSVL015-2016 High-Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations 2016 Abstract | Basepaper
14 ETSVL014-2016 Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications 2016 Abstract | Basepaper
15 ETSVL013-2016 Fault Tolerant Parallel Filters Based On Error Correction Codes 2016 Abstract | Basepaper
16 ETSVL004-2016 A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic 2016 Abstract | Basepaper
17 ETSVL010-2016 An Efficient Constant Multiplier Architecture Based On Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm For Reconfigurable FIR Filter Synthesis 2016 Abstract | Basepaper
18 ETSVL007-2016 A Synergetic Use Of Bloom Filters For Error Detection And Correction 2016 Abstract | Basepaper
19 ETSVL006-2016 A Multi-Cycle Test Set Based On A Two-Cycle Test Set With Constant Primary Input Vectors 2016 Abstract | Basepaper
20 ETSVL003-2016 A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT 2016 Abstract | Basepaper
21 ETSVLSI013 Design Techniques For Low Power High Speed Successive Approximation Analog-to-Digital Converters 2014 Abstract | Basepaper
22 ETSVL029-2016 Recursive Approach To The Design Of A Parallel Self-Timed Adder 2016 Abstract | Basepaper
23 ETSVLSI011 Cordic Iterations Based Architecture For Low Power And High Quality DCT 2014 Abstract | Basepaper
24 ETSVLSI010 Pipelined Radix-2(k) Feedforward FFT Architectures 2014 Abstract | Basepaper
25 ETSVLSI009 An Efficient Systolic Multiplier For GF (2m) Based On All-One Polynomial 2014 Abstract | Basepaper
Next

Corporate Office

  • Eminent Technology Solutions
    BP Plaza,
    91/6, TC Palya Main road,
    Next to RK Apartments,
    Ramamoorthy Nagar,
    Bangalore-560025.
  • 91-95432 18650
  • Email: hrd@eminents.in

Head Office

  • Eminent Technology Solutions
    5 th Floor,Jayam Towers
    HIG 38-80 Feet Road,
    Anna Nagar, Lakshmi Vilas Bank,
    Madurai-625020
  • 91-95432 18650
  • 0452-4353991 / 4354991
  • e-mail : helpdesk@eminents.in